A 0.7 to 3 GHz wireless receiver front end in 65-nm CMOS with an LNA linearized by positive feedback
This paper presents a wireless receiver frontend intended for cellular applications implemented in a 65 nm CMOS technology. The circuit features a low noise amplifier (LNA), quadrature passive mixers, and a frequency divider generating 25 % duty cycle quadrature local oscillator (LO) signals. A complementary common-gate LNA is used, and to meet the stringent linearity requirements it employs posit